1. Field of the Invention
Example embodiments of the present invention relate to a control circuit and method, for example, a multi-threshold complementary metal-oxide semiconductor (MTCMOS) control circuit, and more particularly, to a MTCMOS control circuit which reduces or prevents the performance of a logic circuit from deteriorating due to transistors using MTCMOS technology and/or reduces or minimizes the amount of leakage current when the logic circuit is in sleep mode.
2. Description of the Related Art
In general, in multi-threshold complementary metal-oxide semiconductor (MTCMOS) technology, a metal-oxide semiconductor (MOS) transistor having a relatively high threshold voltage is connected in series between a power supply (or ground) and a logic circuit.
For example, when the logic circuit, which includes a plurality of transistors with a relatively low threshold voltage, is in active mode, e.g., when the logic circuit is powered on, the MOS transistor is turned on, thereby supplying power to the logic circuit and enhancing the operating speed of the logic circuit. When the logic circuit is in sleep mode, e.g., when the logic circuit is powered down, the MOS transistor is turned off, thereby cutting off a power supply voltage or a ground voltage applied to the logic circuit and reducing a leakage current.
Such MTCMOS technology is useful for reducing the power consumption of portable large-scale integration chips which are put into sleep mode for a longer period of time than in active mode.
FIG. 1 is a circuit diagram of a conventional MTCMOS control circuit 100. Referring to FIG. 1, a PMOS transistor MP may be connected in series between a virtual power supply VDDV and a power supply VDD, and an NMOS transistor may be connected in series between a virtual ground VSSV and a ground VSS. A logic circuit 110 may be connected between the virtual power supply voltage VDDV and the virtual ground VSSV. The logic circuit 110 is an example circuit, and may be replaced with any other circuit.
The logic circuit 110 may include a plurality of transistors 111 through 117 and a NAND unit 119. Even though the logic circuit 110 is illustrated in FIG. 1 as including the transistors 111 through 117 and the NAND unit 119, the structure of the logic circuit 110 may be different from the structure illustrated in FIG. 1.
The transistors 111 through 117 and the NAND unit 119 in the logic circuit 110 may have a relatively low threshold voltage. The PMOS transistor MP and the NMOS transistor MN may have a relatively high threshold voltage.
In active mode, the PMOS transistor MP and the NMOS transistor MN may be turned on in response to mode control signals SL and SLB, respectively, the virtual power supply VDDV may be connected to the power supply VDD, and the virtual ground VSSV may be connected to the ground VSS.
Because the transistors 111 through 117 and the NAND unit 119 are lower-threshold voltage devices, the logic circuit 110 may operate with higher performance, a leakage current generated during the operation of the logic circuit 110 may be less than a dynamic current, and thus the leakage current may be ignored.
In sleep mode, the PMOS transistor MP and the NMOS transistor MN may be turned off in response to the mode control signals SL and SLB, respectively, and thus, the logic circuit 110 stops operating. Therefore, no leakage current flows in the logic circuit 110.
Because the PMOS transistor MP and the NMOS transistor MN have a relatively high threshold voltage, the amount of leakage current flowing into the logic circuit 110 via the PMOS or NMOS transistor MP or MN may be reduced. Therefore, the amount of leakage current generated in the logic circuit 110 and/or the power consumption of the logic circuit 110 may be reduced when the logic circuit 110 operates in sleep mode by using the PMOS transistor MP and the NMOS transistor MN.
FIG. 2 is a circuit diagram of a conventional MTCMOS control circuit 200 using a PMOS transistor, and FIG. 3 is a circuit diagram of a conventional MTCMOS control circuit 300 using an NMOS transistor. Referring to FIGS. 2 and 3, logic circuits 210 and 310 may have the same structure as the logic circuit 110 of FIG. 1. Referring to FIG. 2, the MTCMOS control circuit 200 may realize a connection between a virtual power supply VDDV and a power supply VDD, using a PMOS transistor MP. Referring to FIG. 3, the MTCMOS control circuit 300 may realize a connection between a virtual ground VSSV and a ground VSS, using an NMOS transistor MN.
The MTCMOS control circuit 200 may be realized using a well of a PMOS transistor and thus can be manufactured in a conventional bulk method. The MTCMOS control circuit 300 may be manufactured in a method using a well of an NMOS transistor.
For example, the MTCMOS control circuit 300 may be manufactured by a method using a well of an NMOS transistor or using a triple well including a well of a PMOS transistor and a well of an NMOS transistor. The MTCMOS control circuit 100 of FIG. 1 may be obtained by integrating the MTCMOS control circuit 200 of FIG. 2 and the MTCMOS control circuit 300 of FIG. 3 into a single circuit and may be manufactured by a method using a triple well.
However, more leakage current may be generated in the MTCMOS control circuits 100, 200, and 300 of FIGS. 1, 2, and 3, for example, when the transistors in the logic circuits 110, 210, and 310 are manufactured to have a critical dimension of 90 nm or lower. In the active mode, the performance of the logic circuits 110, 210, and 310 may deteriorate due to the reverse body bias effect of the transistors in the logic circuits 110, 210, and 310.
FIG. 4 is a circuit diagram of a logic circuit illustrating one ore more problems with the conventional MTCMOS control circuits 100, 200, and 300 of FIGS. 1, 2, and 3, respectively. Referring to FIG. 4, transistor 117 represents an arbitrary NMOS transistor in a logic circuit. A body of the transistor 117 may be connected to a ground VSS. When the logic circuit operates in active mode, an NMOS transistor MN is turned on in response to a mode control signal SL, and a virtual ground VSSV is connected to a ground VSS. However, the NMOS transistor MN has resistance even when turned on. Thus, the voltage of the virtual ground VSSV becomes slightly higher than the voltage of the ground VSS due to the resistance of the NMOS transistor MN.
For example, if the NMOS transistor MN has a voltage of about 0.1 V due to its resistance, the voltage of the virtual ground VSSV may be higher than the voltage of the ground VSS by about 0.1 V.
Because the body of the transistor 117 is connected to the ground VSS, the voltage between the body and a source of the transistor 117 becomes −0.1 V, thus generating an inverse voltage. This phenomenon is referred to as the reverse body bias effect. Due to the reverse body bias effect, the performance of the transistor 117 may deteriorate and/or the operating speed of a chip including the logic circuit may decrease.
In a case where the transistor 117 is a PMOS transistor, the body of the transistor 117 is connected to the power supply VDD, thereby causing the same problems as in a case where the transistor 117 is an NMOS transistor.